Modern three-dimensional computer graphics use geometry extensively to describe three-dimensional objects, using a variety of graphical representation techniques. Computer graphics find especially wide use in applications such as computer assisted design ("CAD") programs. Complex smooth surfaces of objects to be displayed may be represented using high level abstractions. Detailed surface geometry may be rendered using texture maps, although providing more realism requires raw geometry, usually in the form of triangle primitives.
FIG. 1 depicts a prior art generic video system 10 such as may used with a computer system, e.g., a Sun Micro-systems, Inc. SPARC workstation, to display user-to display user-generated images. Using a drawing program, for example, such images may be created with a mouse, trackball or other user input devices 20 for display on a video monitor 30, among other uses. Within the context of the invention to be described, displayed objects 40, 50 typically will have a three-dimensional surface, and commonly a portion of one object may be hidden by a portion of another object. In FIG. 1, for example, a portion of object 40 appears in front of and thus covers a hidden surface portion of object 50.
Input data from device 20 typically is coupled to a device bus 60, from where coupling to a video processing system 70 occurs, as well as coupling to computer system input/output interface unit 80, and a computer system memory controller unit 90. Units 80 and 90 are typically coupled to a system bus 100 that also is coupled to the system central processor unit ("CPU") 110, and to the computer system persistent memory unit 120. Among other tasks, CPU 110 may be involved with processing triangular data representing the three dimensional surface of the object to be displayed on monitor 30.
CPU-processed video information is coupled via system bus 100, memory controller 90, device bus 60 into video system 70. Video system 70 typically includes a graphics accelerator unit 140, a video frame buffer random access memory unit (e.g., "3DRAM") 150 (or other form of RAM video store) and a video control unit 160. Processed video from video system 70 is then coupled to monitor 30, which displays images such as images 40 and 50.
A so-called Z-buffer unit 144 associated with graphics accelerator unit 130 stores a "Z-value", e.g., a depth-value, for each pixel that is to be rendered and displayed. Pixel values for object 50, for example, should only be overwritten when object 50 is closer to a viewing position than the Z-value that is already stored for that pixel value. The Z-buffer must ensure that objects that are far away from a view point are projected behind objects that are closer to the view point, e.g., portions of object 50 should appear behind object 40, which is nearer to the viewpoint. Further, objects should appear smaller as their distance from the viewpoint increases. The pixel drawing relationship typically is represented by a function that is inversely proportional to distance. This concept is commonly what is meant by Z-buffering, and the Z-data may be referred to as Z-buffered primitives.
Monitor 30 typically is an analog device that requires separate red, blue, green ("R,B,G") input video lines, Thus, frame buffer 150 includes a random access memory digital-to-analog converter ("RAMDAC") 162 that outputs R,B,G analog signals and digital synchronization ("SYNC") signals to the display monitor.
Video control unit 160 typically includes video timing generator 164 and outputs video signals and video timing signals that control movement of video data into and out of frame buffer RAM unit 150.
Unfortunately, the architecture shown in prior art FIG. 1 has been outpaced by the ever increasing demand for faster and more complex display imagery. Displaying three dimensional graphics animation with full color depth simply exceeds the bandwidth of such prior art systems. The result is an unrealistic and jerky sequence of display frames.
There is a need for an architecture for the frame buffer in a video display system that enhances realtime performance of the overall system. Preferably such architecture should be capable of implementation with off-the-shelf generic sub-system components.
The present invention discloses such an architecture.